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CY62138FV30 mobl ? 2-mbit (256 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-08029 rev. *k revised june 16, 2011 2-mbit (256 k 8) static ram features very high-speed: 45 ns temperature ranges ? industrial: ?40 c to 85 c ? automotive-a: ?40 c to 85 c wide voltage range: 2.20 v to 3.60 v pin compatible with cy62138cv25/30/33 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 5 ? a ultra low active power ? typical active current: 1.6 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power offered in pb-free 36-ball vfbga, 32-pin tsop ii, 32-pin soic, 32-pin tsop i and 32-pin stsop packages functional description the CY62138FV30 is a high performance cmos static ram organized as 256k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption. place the device into standby mode reducing power consumption when deselected (ce 1 high or ce 2 low). to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low and ce 2 high and we low). logic block diagram [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 2 of 18 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ........................................................................ 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................. 17 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18 [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 3 of 18 pin configuration figure 1. 36-ball vfbga (top view) [1] figure 2. 32-pin soic/tsop ii (top view) figure 3. 32-pin tsop i (top view) figure 4. 32-pin stsop (top view) a 15 v cc a 13 a 12 a 5 ce 2 we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 nc a 16 ce 1 oe a 9 a 14 d e b a c f g h nc 3 2 6 5 4 1 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ss v cc ce 2 we oe ce 1 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 a 17 a 10 i/o 3 a 1 a 0 a 3 a 2 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe stsop top view (not to scale) 30 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 9 10 32 1 2 3 4 5 6 7 8 ce 2 a 15 a 17 a 10 i/o 3 a 1 a 0 a 3 a 2 26 25 26 27 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max CY62138FV30ll industrial / automotive-a 2.2 3.0 3.6 45 1.6 2.5 13 18 1 5 notes 1. nc pins are not connected on the die. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 4 of 18 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential .................................... .....................?0.3 v to 3.9 v dc voltage applied to outputs in high z state [3, 4] ........................................?0.3 v to 3.9 v dc input voltage [3, 4] .....................................?0.3 v to 3.9 v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................ > 2001 v (mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range product range ambient temperature v cc [5] CY62138FV30ll industrial / automotive-a ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns (industrial / automotive-a) unit min typ [6] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 v i ol = 2.1 ma, v cc > 2.70 v ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v v v il input low voltage v cc = 2.2 v to 2.7 v for bga package ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v v cc = 2.2 v to 3.6 v for other packages ?0.3 ? 0.6 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax , i out = 0 ma, cmos levels ?1318ma f = 1 mhz ? 1.6 2.5 i sb1 [7] automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , and we ), v cc = 3.60 v ?15 ? a i sb2 [7] automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?15 ? a notes 3. v il(min) = ? 2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 7. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 5 of 18 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ.) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 32-pin soic 36-ball vfbga 32-pin tsop ii 32-pin stsop 32-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two layer printed circuit board 44.53 38.49 44.16 59.72 50.19 ? c/w ? jc thermal resistance (junction to case) 24.05 17.66 11.97 15.38 14.59 ? c/w ac test loads and waveforms figure 5. ac test loads and waveforms parameter 2.5 v (2.2 v to 2.7 v) 3.0 v (2.7 v to 3.6 v) unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 note 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 6 of 18 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current v cc = 1.5 v, ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v, v in > v cc ?? 0.2 v or v in < 0.2 v industrial / automotive-a ?14 ? a t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time 45 ? ? ns data retention waveform figure 6. data retention waveform [13] v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce notes 9. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 10. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 13. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 7 of 18 switching characteristics over the operating range parameter [14] description 45 ns (industrial/ automotive-a) unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ?45ns t doe oe low to data valid ?22ns t lzoe oe low to low z [15] 5?ns t hzoe oe high to high z [15, 16] ?18ns t lzce ce 1 low and ce 2 high to low z [15] 10 ? ns t hzce ce 1 high or ce 2 low to high z [15, 16] ?18ns t pu ce 1 low and ce 2 high to power-up 0?ns t pd ce 1 high or ce 2 low to power-down ?45ns write cycle [17] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0?ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0?ns t hzwe we low to high z [15, 16] ?18ns t lzwe we high to low z [15] 10 ? ns notes 14. test conditions for all parameters other than tristate paramete rs assume signal transition time of 3 ns or less (1 v/ns), ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ac test loads and waveforms on page 5 . 15. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 16. t hzoe , t hzce , and t hzwe transitions are measured when the output enters a high impedance state. 17. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. reference the data input setup and hold timing to the edge of the signal that terminates the write. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 8 of 18 switching waveforms figure 7. read cycle 1 (address transition controlled) [18, 19] figure 8. read cycle no. 2 (oe controlled) [19, 20, 21] figure 9. write cycle no. 1 (we controlled) [21, 22, 23, 24] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 25 notes 18. the device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 19. we is high for read cycle. 20. address valid before or similar to ce 1 transition low and ce 2 transition high. 21. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 22. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. reference the data input setup and hold timing to the edge of the signal that terminates the write. 23. data i/o is high impedance if oe = v ih . 24. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 25. during this period, the i/os are in output state. do not apply input signals. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 9 of 18 figure 10. write cycle no. 2 (ce1 or ce2 controlled) [26, 27, 28, 29] figure 11. write cycle no. 3 (we controlled, oe low) [26, 29] truth table ce 1 ce 2 we oe inputs/outputs mode power hx [31] x x high z deselect/power-down standby (i sb ) x [31] l x x high z deselect/power-down standby (i sb ) l h h l data out read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in write active (i cc ) switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 30 notes 26. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 27. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. reference the da ta input setup and hold timing to the edge of the signal that terminates the write. 28. data i/o is high impedance if oe = v ih . 29. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains iin high impedance state. 30. during this period, the i/os are in output state. do not apply input signals. 31. the ?x? (don?t care) state for the chip enables (ce 1 and ce 2 ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted. [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 10 of 18 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62138FV30ll-45bvxi 51-85149 36- ball vfbga (pb-free) industrial CY62138FV30ll-45zsxi 51-85095 32-pin tsop ii (pb-free) CY62138FV30ll-45zaxi 51-85094 32-pin stsop (pb-free) CY62138FV30ll-45zxi 51-85056 32-pin tsop i (pb-free) CY62138FV30ll-45sxi 51-85081 32-pin soic (pb-free) CY62138FV30ll-45zaxa 51-85094 32-pin stsop (pb-free) automotive-a ordering code definitions temperature grade: x = i or a i = industrial; a = automotive-a pb-free package type: xx = bv or zs or za or z or s bv = 36-ball vfbga zs= 32-pin tsop ii za = 32-pin stsop z = 32-pin tsop i s = 32-pin soic speed grade: 45 ns ll = low power voltage range: 3 v typical f = process technology 90 nm buswidth = 8 density = 2-mbit family code: mobl sram family company id: cy = cypress cy 45 xx 621 3 8 f x ll x - v30 [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 11 of 18 package diagrams figure 12. 36-ball vfbga (6 8 1.0 mm) bv36a, 51-85149 51-85149 *d [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 12 of 18 figure 13. 32-pin tsop ii (20.95 11.76 1.0 mm) zs32, 51-85095 51-85095 *b [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 13 of 18 figure 14. 32-pin molded soic (450 mil) s32.45/sz32.45, 51-85081 51-85081 *c [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 14 of 18 figure 15. 32-pin tsop i (8 20 1.0 mm) z32, 51-85056 51-85056 *f [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 15 of 18 figure 16. 32-pin stsop (8 13.4 1.2 mm) za32, 51-85094 51-85094 *f [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 16 of 18 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor i/o input/output oe output enable soic small-outline integrated circuit sram static random access memory stsop small thin small outline package tsop thin small outline package vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz mega hertz ? a micro amperes ? s micro seconds ma milli amperes mm milli meter ns nano seconds ? ohms % percent pf pico farads v volts w watts [+] feedback
CY62138FV30 mobl ? document #: 001-08029 rev. *k page 17 of 18 document history page document title: CY62138FV30 mobl ? , 2-mbit (256 k 8) static ram document number: 001-08029 rev. ecn no. submission date orig. of change description of change ** 463660 see ecn nxr new data sheet *a 467351 see ecn nxr added 32-pin tsop ii package, 32 pin tsop i and 32 pin stsop packages changed ball a3 from nc to ce 2 in 36-ball fbga pin out *b 566724 see ecn nxr converted from preliminary to final corrected typo in 32 pin tsop ii pin conf iguration diagram on page #2 (changed pin 24 from ce 1 to oe and pin 22 from ce to ce 1 ) changed the i cc(max) value from 2.25 ma to 2.5 ma for test condition f=1 mhz changed the i sb2(typ) value from 0.5 ? a to 1 ? a changed the i sb2(max) value from 2.5 ? a to 5 ? a changed the i ccdr(typ) value from 0.5 ? a to 1 ? a and i ccdr(max) value from 2.5 ? a to 4 ? a *c 797956 see ecn vkn added 32-pin soic package updated vil spec for soic, tsop-ii, tsop-i, and stsop packages on electrical characteristics table *d 809101 see ecn vkn corrected typo in the ordering information table *e 940341 see ecn vkn added footnote #7 related to i sb2 and i ccdr *f 2769239 09/25/09 vkn/aesa included automotive-a information *g 3055119 10/12/2010 rame updated and conv erted all tablenotes into footnote added acronyms and units of measure table added updated all package diagrams . updated datasheet as per new template. *h 3061313 10/15/2010 rame minor cha nges: corrected ?io? to ?i/o? *i 3078557 11/04/2010 rame corrected 55 c to -55c in ambient temperature with power applied in maximum ratings section *j 3235744 04/20/2011 rame removed the note ?for best practice recommendations, refer to the cypress application note ?system design guidelines? at http://www.cypress.com ? in page 1 and its reference in functional description . updated package diagrams . *k 3285093 06/16/2011 rame updated in new template. [+] feedback
document #: 001-08029 rev. *k revised june 16, 2011 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. CY62138FV30 mobl ? ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representati ves, and distributors. to find th e office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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